1. Field of the Invention
The present invention relates to a semiconductor memory, or more particularly, to a circuit technology preferred for shortening a delay time required by a sense amplifier.
2. Description of the Related Art
Numerous sense amplifiers have been proposed for quickly amplifying a small signal output from a memory cell of a semiconductor memory. Sense amplifiers that can amplify a signal most quickly include a circuit disclosed in the digest of technical papers published at the IEEE International Solid-state Circuits Conference for 1998 pp. 360-361.
FIG. 1 is a circuit diagram concerning the related art. In FIG. 1, there are shown memory cells MC0, etc., and MCn, bit line select Y switches MYL and MYR. Bit line select signals YS0, etc., and YSn are used to control the Y switches. Transistors MPL, MPR, and ME constitute a precharge circuit for precharging common data lines CDL and CDR. A precharge control signal CDE is used to precharge the common data lines. A circuit composed of transistors M10 to M16 is a first-stage sub-sense amplifier. A circuit composed of transistors M20 to M27 is a second-stage sub-sense amplifier. Also shown are a sense amplifier activating signal SC, inverters IV0 and IV1, and a sense amplifier output node SQ.
Referring to FIG. 2 showing waveforms (solid lines) that indicate actions to be performed, a description will be made of the actions to be performed in the circuitry of the related art shown in FIG. 1.
At time instant t0, the precharge control signal CDE is low. The common data lines CDL and CDR are precharged and the potentials on the common data lines are driven high. Moreover, the sense amplifier activating signal SC is low. The sense amplifier is on standby.
Thereafter, the Y switches are turned on. At time instant t4, the precharge control signal CDE is driven high. The potential on one of the common data lines CDL and CDR starts dropping according to information stored in a selected memory cell (in this example, the potential on the common data line CDL drops).
Thereafter, at time instant t6, the sense amplifier activating signal SC is driven high in order to activate the sense amplifier. The potential on one of output signal lines SQAL and SQAR extending from the first-stage sub-sense amplifier starts dropping (in this example, the potential on the output signal line SQAL drops).
A potential difference between the output signal lines SQAL and SQAR is amplified by the second-stage sub-sense amplifier, and then applied to the sense amplifier output node SQ via the inverters IV0 and IV1. In this example, the potential difference between the output signal lines SQAL and SQAR becomes equal to nearly a half of a supply voltage VDD at time instant t8. The potential at the sense amplifier output node SQ is driven low.
Thereafter, the precharge control signal CDE is driven low at time instant t10. The common data lines CDL and CDR are precharged and have the potential thereon brought back to high. When the sense amplifier activating signal SC is driven low (time instant t10), the potentials on the output signal lines SQAL and SQAR are brought back to high. The sense amplifier re-enters a standby state.
At time instant t12, the sense amplifier output node (hereinafter, simply, output node) SQ is brought back to high.
Thereafter, the next cycle starts at time instant t14. The same actions as those of the first cycle start. In this example, information stored in a memory cell selected for the second cycle is opposite to information stored in the memory cell selected for the first cycle. Therefore, when the precharge control signal CDE is driven high at time instant t14, the potential on the common data line CDR drops.
When the sense amplifier activating signal SC is driven high at time instant t16 in order to activate the sense amplifier, the potential on the output signal line SQAR starts dropping. During the second cycle, the relationship between the potentials on the output signal lines SQAL and SQAR is opposite to that attained during the first cycle. The potential at the output node SQ remains high.
A circuit in the next stage for inputting the potential at the output node SQ can read information stored in a selected memory cell by detecting whether the potential at the output node SQ goes low or remains high.
As mentioned above, according to the circuitry of the related art shown in FIG. 1, the sense amplifier is composed of two sub-sense amplifiers in efforts to realize fast reading.
However, the conventional sense amplifier suffers from an offset voltage derived from differences in properties of transistors constituting the sense amplifier. Limitations are therefore imposed on fast reading, which will be described below.
In the circuitry of the related art shown in FIG. 1, the first-stage sub-sense amplifier suffers from an offset voltage. When the activating signal SC is driven high in order to activate the sense amplifier, even if a potential difference between the common data lines CDL and CDR is zero, one of the potentials on the output signal lines SQAL and SQAR starts dropping without fail. Hereinafter, assume that the potential on the output signal line SQAL drops.
FIG. 2 shows waveforms indicating actions to be performed when the timing of activating the sense amplifier using the activating signal SC is advanced because of a variation in temperature or supply voltage. Assume that the timing of activating the sense amplifier with the activating signal SC driven high is advanced from time instant t6 to time instant t2. Although a potential difference between the common data lines CDL and CDR is zero, the potential on the output signal line SQAL starts dropping because of an offset voltage. A potential difference between the output signal lines SQAL and SQAR is amplified by the second-stage sub-sense amplifier, and applied to the output node SQ via the inverters IV0 and IV1.
In this example, when the potential difference between the output signal lines SQAL and SQAR becomes equal to nearly a half of the supply voltage VDD at time instant t4, the potential at the output node SQ is driven low. Therefore, as far as the first cycle is concerned, when the timing of activating the sense amplifier using the activating signal SC is advanced, the potential at the output node SQ is reversed earlier. Thus, reading appears to be speeded up.
However, a problem occurs during the second cycle. Assume that the timing of activating the sense amplifier with the activating signal SC driven high is advanced from time instant t16 to time instant t12 during the second cycle. In this case, although a potential difference between the common data lines CDL and CDR is zero, the potential on the output signal line SQAL starts dropping because of an offset voltage in the same manner as it is during the first cycle. A potential difference between the output signal lines SQAL and SQAR is amplified by the second-stage sub-sense amplifier, and applied to the output node SQ via the inverters IV0 and IV1. The potential difference between the output signal lines SQAL and SQAR becomes equal to nearly a half of the supply voltage at time instant t14. Consequently, the potential at the output node SQ is driven low. This causes the circuit in the next stage for detecting whether the potential at the output node SQ goes low or remains high to malfunction.
For speeding up the reading action of the sense amplifier, the timing of activating the sense amplifier should be advanced. However, if the timing is too early, a malfunction occurs because of a variation in temperature or supply voltage. Namely, an offset voltage occurs because of the differences in properties of transistors constituting the sense amplifier, limitations are imposed on fast reading.